The present invention relates to the structure and fabrication of semiconductor devices.
In fabricating integrated circuits in conventional bulk semiconductor wafers, wells of either p-type or n-type conductivity are implanted in a substrate of the opposite conductivity. However, in complementary metal oxide semiconductor (CMOS) technology, both p-type and n-type wells are utilized. Source/drain regions are formed by implanting diffusion regions of the opposite n-type or p-type conductivity as the wells to form metal-oxide-semiconductor field effect transistors (MOSFETs). Recent theoretical and empirical studies have also demonstrated that carrier mobility in a transistor can be increased when a stress of sufficient magnitude is applied to the conduction channel of a transistor to create a strain therein. An increase in the performance of an n-type field effect transistor (NFET) can be achieved by applying a tensile longitudinal stress to the conduction channel of the NFET. An increase in the performance of a p-type field effect transistor (PFET) can be achieved by applying a compressive longitudinal stress to the conduction channel of the PFET.
A stress-imparting film, also referred to herein as a “stressed” film, can be deposited to cover a semiconductor device region to impart a stress thereto for enhancing the conductivity of a transistor, for example, an NFET or a PFET device. Silicon nitride is one material, among others, which can be deposited in such way that the resulting material layer imparts either a tensile stress or a compressive stress to a layer of a second material with which it is in contact. To improve the conductivity of both an NFET and a PFET, a tensile stress-imparting nitride can be formed to cover an NFET device region and a compressive stress-imparting nitride can be formed to cover a PFET device region.
From a fabrication point of view, such a goal can be accomplished by applying two films, each having a different internal stress. In such case, one film 102 can be patterned, after which a second film 104 is deposited and then patterned to produce an overlapped boundary 100, as illustrated in the cross-sectional depiction of FIG. 1. An overlapped boundary, however, can create certain problems.
One such problem concerns the fabrication of a contact via 210 to a current-conducting member, e.g., a silicided polysilicon conductor 225, at a location overlying a shallow trench isolation (STI) region 110, i.e., at the boundary 220 between two differently stressed films. The etching of the contact hole at that boundary 220 can be very difficult to perform while etching other contact holes, such as the contact hole for contact via 212 to the polysilicon conductor 225. The difficulty arises because of the variation in thickness between the film 104 which overlies the silicided polyconductor 225 where the contact via 212 is formed, as compared to the combined thickness of the stressed film 104 together with the stressed film 102, which it overlaps at the boundary 220. As apparent from FIG. 1, the overlapped stressed films 102, 104 at the boundary 220 are much thicker than the film 104 where the contact via 212 is formed. Due to the variation in the total film thicknesses, there is increased likelihood that the etching of the contact hole for contact via 210 will fail to be etched to a sufficient depth to properly contact the silicided polysilicon conductor 225. Indeed, a contact open failure can result, as best seen at 220 in FIG. 2. A contact open failure is one in which much higher than normal contact resistance occurs at the interface between the conductive contact via and the polysilicon conductor. A contact open failure can occur when the contact hole fails to be etched sufficiently.
Consequently, a need exists for a structure and an associated method of fabricating a semiconductor device in which more than one stressed films can be provided, while permitting contact vias to be etched with less difficulty.